1. Field of the Invention
The present invention relates to a starter circuit that is formed in a semiconductor integrated circuit and that generates a starter signal, which initializes the circuits internal to the integrated circuit when the semiconductor integrated circuit is in power up condition.
2. Description of the Related Art
In general, a semiconductor integrated circuit incorporates a starter circuit that generates a starter signal. Prevention of malfunction of the semiconductor integrated circuit is realized by initializing the internal circuit of the semiconductor integrated circuit, utilizing a time period from power-up until the generation of a starter signal. This kind of starter circuit utilizes the threshold voltages of transistors to detect that the power supply voltage rises to a predetermined value and change the logic level of the starter signal. The internal circuit having latches or the like is initialized before the generation of the starter signal and start its normal operation after the generation of the starter signal.
FIG. 1 shows a starter circuit disclosed in Japanese Unexamined Patent Application Publication No. 2000-165220. This starter circuit includes a voltage generating unit 10, a starter signal generating unit 12, and a waveform shaping circuit 14 that outputs a starter signal STT.
The voltage generating unit 10 has resistors R1 and R2 and an nMOS transistor M1 connected in series between a power supply line VDD and a ground line VSS. The gate and drain of the nMOS transistor M1 are connected to each other. The voltage at a connection node ND1 between the resistors R1 and R2 in the voltage generating unit 10 rises with a rise of the power supply voltage VDD until it exceeds the threshold voltage of the nMOS transistor M1. After the voltage at the node ND1 exceeds the threshold voltage of the nMOS transistor M1, it rises as a voltage obtained by adding the threshold voltage to the voltage obtained by dividing the voltage difference between the power supply voltage VDD and the threshold voltage.
The starter signal generating unit 12 has a resistor R3 and an nMOS transistor M2 connected in series between the power supply line VDD and the ground line VSS. The gate of the nMOS transistor M2 is connected to the node ND1. The voltage at a connection node ND2 between the resistor R3 and the nMOS transistor M2 rises with the rising power supply voltage VDD until the nMOS transistor M2 is turned on. After the nMOS transistor M2 is turned on, the voltage at the node ND2 becomes equal to the ground voltage VSS.
The waveform shaping unit 14, which has three inverters in a cascade connection, generates the starter signal STT in accordance with the voltage generated at the node ND2.
In the starter circuit as described above, when the threshold voltage of the nMOS transistor M1 is high, the voltage as divided at the node ND1 is high. Conversely, when the threshold voltage of the nMOS transistor M1 is low, the voltage as divided at the node ND1 is low. In a typical semiconductor integrated circuit, the threshold voltages of adjacent transistors exhibit the same value. For this reason, when the threshold voltage of the nMOS transistor M1 is high, that of the nMOS transistor M2 is also high. Thus, when the threshold voltage of the nMOS transistor M2 is high, the voltage at the node ND1 is high, and when the threshold voltage of the nMOS transistor M2 is low, the voltage at the node ND1 is low. In this way, varying the gate-to source voltage of the nMOS transistor M2 in accordance with the threshold voltage thereof allows the starter signal STT to be generated nearly at a predetermined timing (a predetermined power supply voltage VDD), hardly being affected by the threshold voltage of the nMOS transistor M2.
Recently, semiconductor integrated circuits have been designed to consume a lower operating voltage and hence receive a lower power supply voltage VDD from the exterior of the semiconductor integrated circuits. The threshold voltages of the transistors are hardly dependent on the power supply voltage VDD. For this reason, as the power supply voltage VDD becomes lower, the ratio of the threshold voltages of the transistors to the power supply voltage VDD becomes larger, with the result that the deviation of the timing of generation of the starter signal STT caused by a variation in the threshold voltages becomes relatively large. That is, it has become difficult to generate the starter signal STT at a predetermined timing.
As the power supply voltage VDD becomes lower, the time period in which the power supply line of the internal circuit reaches the power supply voltage VDD at power-up becomes shorter. It is, therefore, necessary to shorten the time period in which the starter signal STT is generated after power-up (the time period required to initialize the internal circuit). On the other hand, if the time period required to initialize the internal circuit is not adequately obtained, there is a fear that the internal circuit is not initialized, resulting in a malfunction of the semiconductor integrated circuit. In order to ensure that the internal circuit is initialized, the time period for initializing the internal circuit must be elongated as much as possible.
It is an object of the present invention to ensure that, even when the power supply voltage is low, the starter signal is generated and the internal circuit of the semiconductor integrated circuit is initialized.
According to one of the aspects of the starter circuit of the present invention, a voltage generating unit has a plurality of first resistors and a first transistor connected in series between a first power supply line and a second power supply line. The voltage generating unit generates a first voltage at a first node where resistive division is made by the first resistors. A gate of the first transistor is always supplied with a voltage higher than a drain voltage thereof. That is, the source-to-gate voltage of the first transistor is higher than in the conventional art, and the on-resistance of the first transistor is lower. For this reason, the first voltage that is generated at the first node after the power supply voltage exceeds the threshold voltage of the first transistor at power-up and the first transistor is turned on is lower than in the conventional art. That is, the first voltage gently rises, as compared with that in the conventional art.
A starter signal generating unit has a second resistor and a second transistor connected in series between the first and second power supply lines. The gate of the second transistor is connected to the first node. The starter signal generating unit generates, in accordance with the first voltage of the first node, a second voltage at a second node connecting the second resistor with the second transistor. Specifically, when the first voltage exceeds the threshold voltage of the second transistor, the logic level of the second voltage is reversed. Since the first voltage gently rises, the timing of reversing the logic level of the second voltage is delayed compared to that in the conventional art.
A waveform shaping unit shapes a waveform of the voltage of the second node and outputs a shaped waveform as a starter signal that initializes an internal circuit of an integrated circuit. Since the timing of reversing the logic level of the second voltage is delayed compared to that in the conventional art, the time period from the power-up until the output of the starter signal is longer than in the conventional art. Consequently, even when the power supply voltage is low, the time period that is long enough to initialize the internal circuit of the semiconductor integrated circuit can be obtained, thereby initializing the internal circuit without fail.
According to another aspect of the starter circuit of the present invention, the first transistor is connected its gate to any one of the nodes where resistive divisions are made, respectively, by the first resistors. Consequently, the gate voltage of the first transistor can be maintained constantly higher than the drain voltage thereof, without forming any special circuit.